MiSTer FPGA Input Latency Explorer
Browse controller latency measurements - recorded on MiSTer FPGA, but applicable to devices that poll USB at 1 ms.
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Source data: Open the input latency spreadsheet.
Looking for core releases instead? Open the MiSTer Core Explorer.
Testing Methodology
Each input device is measured on MiSTer at a 1 ms USB polling interval. An ATMega 32u4 microcontroller is wired directly to a button on the controller PCB, then commands randomized button presses by pulling that button line to ground and releasing it.
The controller is connected to MiSTer over USB or its wireless receiver. A custom MiSTer NES core raises a signal on a User I/O pin when the USB button press is detected, and the microcontroller records the elapsed time from commanded press to MiSTer detection.
CSV captures are summarized with R to calculate average latency, distribution statistics, sample count, and percentile data when raw captures are available. MiSTer was chosen for deterministic FPGA GPIO and a low-latency USB stack; at 1 ms polling, the theoretical average floor is 0.5 ms, with the fastest measured devices landing around 0.7 ms.
Tester files are available in the inputlatency GitHub repository, including the NES_Lag_Tester.rbf MiSTer core. The current source spreadsheet is available in Google Sheets.
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Compare average latency and consistency
Each point is an input device. X is average latency on a logarithmic scale; Y is same-frame probability derived from average latency. Hovering over dense areas fans points horizontally and lifts them in a tapered arc for selection.